信号完整性工程师岗位职责

信号完整性工程师 捷普集团 JABIL 绿兴(无锡)电子科技有限公司,绿兴 JSUMMARY

概述

Take the major responsibility for Signal integrity design for Server, Storage, and networking switch projects. Provide necessary inputs regarding high-speed signal quality and design constraints to electronics designers for signal design quality assurance. Drive innovation and continuous improvement within Jabil Circuit by harnessing new technologies and methodologies. Provide exceptional support to external and internal customers, team members, and other persons through technical project coordination.

ESSENTIAL DUTIES AND RESPONSIBILITIES include the following. Other duties may be assigned.

主要责任包括以下所列及其他:

 Responsible for the high-speed signal pre-simulation and post-simulation, layout constraints preparation, and PCB stackup design.

 Perform system level’s signal integrity and timing analysis on boards, packages, connectors and ASICs etc。

 Cooperate with SPIT(Signal, Power Integrity Test) engineers to develop SPIT test plans

 Correlate SI simulations with SPIT measurements to validate the modeling methodology

 Contribute to the design trade-offs and eva luation of mechanical, electrical, and thermal performance of both components level and system level

 Cooperate with electronics engineers for signal issues Lab debug

 Develop quotations ands schedules for development programs with little or no assistance.

在很少或没有协助的情况下,提出开发计划的报价和时间进度。

 Work concurrently with Jabil CAD Services, Business Unit Management, Manufacturing, Test, Purchasing, and Quality departments through the design phase of a program. Work to provide a design that not only meets the customer’s criteria, but is also of high quality, cost effective, and manufacturable.

在整个项目设计阶段与捷普的CAD服务、商务管理、制造、测试、采购、以及质量等部门共同工作,提供既能满足用户标准、又能满足高质量、低成本、可制造的设计。

 Provide Business Unit Management / Business Development with timely and accurate design quotations to aid in the quoting process.

协助在报价阶段向商务管理/商务开发部门提供及时准确的设计报价

 Help Business Unit Management / Business Development in the decision of the feasibility and technological merit of new opportunities.

帮助商务管理/商务开发部门进行新机会的可行性与科技价值决策

 Support production discrepancies by incorporating fixes into subsequent revisions in a timely manner.

对由于后续版本改进而引入的生产上的差异提供及时支持

 Record all ideas, sketches, and pertinent conversations in Design Engineering approved Log Book or Design Notebook.

在核准的设计工程日志本中记录所有的观点、草图、以及相关的会谈情况

 Use SPC data collected in production in subsequent programs to ensure continuing improvement in designs.

利用生产过程中收集的SPC数据在随后的过程中确保设计的不断改进

 Be responsible for directing the Design Technicians on their assigned projects.

负责设计技术人员在其分配项目中的指导

 Stay abreast of the latest technology and techniques to provide designs that are competitive and cost effective.

与最新的技术和工艺保持同步以使提出的设计具有竞争力和成本效益

 Exercises judgment within defined procedures and practices to determine appropriate action.

在规定的流程和实践中实施判断并采取适当的行动

 Adhere to all safety and health rules and regulations associated with this position and as directed by supervisor.

根据主管的指示,遵守与这个职位相关的所有安全卫生的规章制度。

 Comply and follow all procedures within the company security policy.

遵守公司安全政策的流程

MINIMUM REQUIREMENTS

基本要求

 Bachelor's degree, master’s preferred, in Engineering or Equivalent with 4+ years related experience in PC/Server/Storage high signal simulation

 Proficient with board level’s reflection, cross-talk, ground bounce, bypassing techniques for power/ground noise reduction, termination techniques for reflection noise control

 Proficient with on chip SI including core noise modeling, on chip crosstalk, I/O selection, chip pin-out assignment, package selection and pin-out arrangement

 Proficient with PCB cross-section design and trade-off, SERDES channel analysis and PCB stack-up calculation etc.

 Proficient with 2-D/3-D CAD tools such as Allegro and Mentor and competent for SPIT (Signal/Power Integrity Test) Measurement

 Good working knowledge in various electronics test and measurement instruments like signal generators, logic analyzer, network analyzer, bus protocols analyzer, and oscilloscope etc.

 Familiar with PCIE Gen3/4, DDRx, Clock SAS/SATA, and other SerDES signal integrity and power plane DC drop simulation

 Preferred Knowledge

 Experience of working in medium sized multidisciplinary development teams

 Good English Speaking and literacy

 The successful candidate will be a self-motivated individual capable of working with a minimum of supervision in a dynamic team environment. Good interpersonal skills: be able to communicate in English with members of other teams, departments and clients; as a high degree of liaison is needed.